The present invention relates to a method of manufacturing a capacitor in a semiconductor device. More particularly, the present invention relates to a method of manufacturing a capacitor in a semiconductor device using a metal compound having a relatively high melting-point.
With ever increasing integration of semiconductor devices and particularly semiconductor memory devices, both the size of device components and the power supply voltage applied to these components have decreased. More specifically, as integration of semiconductor devices increases, the surface area of capacitor electrodes in the semiconductor devices decreases accordingly. Unfortunately, as the surface area of capacitor electrodes decreases, the overall electrostatic capacity of the capacitor also decreases. Additionally, as power supply voltages decrease with increasing integration of semiconductor devices in order to improve device reliability, the electrostatic capacity of the capacitor further decreases. Thus, conventional capacitor structures and conventional methods of fabricating semiconductor capacitors have proved increasingly unsatisfactory.
In attempts to remedy the foregoing problems, new capacitor structures, such as the cylindrical three-dimensional structure, with increased electrode surface areas having been proposed. Further, dielectric layers formed from materials having higher dielectric constants have been used. For example, the conventional silicon oxide or nitride dielectric layers have been replaced by layers formed from tantalum pentoxide (Ta.sub.2 O.sub.5) or BST ((Ba, Sr)TiO.sub.3)).
FIGS. 1A and 1B are section views illustrating a conventional method of manufacturing a capacitor having a dielectric layer formed from one of these higher dielectric materials. Referring to FIG. 1A, a patterned insulating layer 11 is formed on a semiconductor substrate 10 by deposition of an oxide layer, for example, and selective etching of the insulating layer through a photolithography process to form contact holes exposing predetermined portions of substrate 10. Thereafter, a conductive layer, such as a polysilicon layer doped with phosphorous (P), is used to form a lower electrode 12 of a capacitor. The conductive layer is deposited over the entire surface of the patterned insulating layer 11 filling the contact holes. The conductive layer is then patterned using known photolithography processes to form lower electrode 12 of the capacitor.
Referring to FIG. 1B, a tantalum pentoxide layer or a BST layer is deposited as a capacitor dielectric layer 13 over the surface of the resultant structure following formation of lower electrode 12. Then, a polysilicon layer or a metal layer such as titanium nitride (TiN), tungsten nitride (WN) or tungsten (W) is deposited over dielectric layer 13, thereby forming an upper electrode 14 of the capacitor.
However, this conventional method of manufacturing a semiconductor capacitor is not without its problems. When tantalum pentoxide is used as the capacitor dielectric layer and polysilicon is used to form the upper and lower electrodes, oxygen from the tantalum pentoxide diffuses out and reacts with the polysilicon. This reaction forms an oxide layer at the interface between the dielectric layer and the opposing electrodes. As a result, tantalum (Ta) in the tantalum pentoxide layer assumes a stoichiometrically surplus state with respect to the out-diffused oxygen. This unstable structure tends to increase leakage current in the resulting capacitor.
In order to prevent this problem, efforts have been made to use a metal electrode without the undesired oxidizing properties. However, use of a single thin metal layer as the lower electrode often results in lifting of the thin metal layer during subsequent processing. This is particularly true when attempts are made to use the thin metal layer in complex capacitor structures like the cylindrical three-dimensional structure. Lifting of the thin metal layer results in the development of severe peaks and depressions in the capacitor structure. Such structural anomalies can not be tolerated in highly integrated semiconductor devices.
Thus, to prevent this phenomenon, a method of depositing a metal layer such as TiN, WN, tungsten silicide (WSi) over the structure of a completed lower electrode has been adopted. However, this method requires additional steps to separate and isolate adjacent metal layer over capacitors arranged with increasingly narrow separation intervals. Such additional steps are costly and difficult to perform.